1. Field of the Invention
The present invention relates to a low pass filter, and in particular to a low pass filter used to smooth variations in a voltage provided to a voltage regulator.
2. Discussion of the Related Art
Voltage regulators are well known in the art of integrated circuits (ICs). A voltage regulator is a device that takes an input voltage and conditions it to provide a better-controlled output voltage. This conditioning is important, particularly if the input voltage fluctuates. Specifically, a voltage regulator is often used to ensure that a relatively constant regulated voltage is provided to the voltage-sensitive internal circuits of the IC.
Some of these circuits are especially sensitive to variations in the regulated voltage. One such circuit is the delay locked loop (DLL) in the Virtex(trademark) field programmable gate array (FPGA) sold by Xilinx, Inc. DLLs are used in digital systems to minimize clock skew. DLLs typically use delay elements to synchronize the active edges of a reference clock signal in one part of the system with a feedback clock signal from a second part of the system. A detailed description of the Virtex DLL is provided in U.S. patent application Ser. No. 09/102,740, entitled xe2x80x9cDelay Lock Loop With Clock Phase Shifterxe2x80x9d, filed on Jun. 22, 1998 and incorporated by reference herein.
An abrupt change in the regulated voltage to a DLL would contribute to DLL output jitter, or possibly loss of lock, both of which are highly undesirable. Specifically, any clock skew not corrected by the DLL can cause a digital system to malfunction. Therefore, a need arises for a way to minimize abrupt changes in the regulated voltage provided by the voltage regulator.
In accordance with one embodiment of the present invention, a low pass filter (LPF) is provided between a reference voltage circuit and the voltage regulator. The LPF smoothes and significantly slows any change in the reference voltage, which in turn eliminates any abrupt change in the regulated voltage. Thus, the present invention advantageously minimizes the possibility of a malfunction in a digital system due to a variation in the regulated voltage.
The LPF of the present invention includes a circuit having both a resistance and a capacitance. In one embodiment, the resistance (R) of the LPF is provided by a plurality of series-connected PMOS transistors. In another embodiment, a single PMOS transistor is used. In either embodiment, the gate of each PMOS transistor is coupled to ground and therefore each PMOS transistor is conducting. In this configuration and with appropriate sizing, the PMOS transistor(s) will form a large resistor. The capacitance (C) of the LPF is provided by an NMOS transistor having its source and drain tied to ground. In this configuration, the NMOS transistor forms a capacitor. The NMOS transistor is coupled to the PMOS transistor(s) to form the RC circuit which implements the LPF.
Of importance, each PMOS transistor in the LPF of the present invention is fabricated in a floating well. Therefore, the LPF of the present invention eliminates any capacitive coupling between a voltage supply and the well. In this manner, any variation in the supply voltage fails to affect adversely the output voltage of the LPF. Thus, the LPF of the present invention can advantageously smooth and significantly slow any change in the reference voltage. The voltage regulator, which receives the filtered reference voltage, in turn provides a significantly more constant regulated voltage to the internal circuits of the IC.
In one embodiment of the present invention, the source and drain terminals of a bypass transistor are coupled to either side of the series-connected PMOS transistors. During power-up, this bypass transistor is turned on, thereby allowing the voltage regulator to see immediately the reference voltage. After power-up is completed, the bypass transistor is turned off, thereby ensuring that the LPF filters the reference voltage.